Makefile

Here is a simple Makefile which could be a good starting point:

#!/usr/bin/env make

CFLAGS += -Wall -Wextra
CFLAGS += -Iinclude
-include .makerc

csrc := $(wildcard src/*.c) $(wildcard src/**/*.c)
obj := $(csrc:%.c=obj/%.o)
obj/%.o: %.c
	@mkdir -p "$(@D)"
	@$(CC) -c $(CFLAGS) $< -o $@

lib/obj.so: $(filter-out obj/src/main.o,$(obj))
	@mkdir -p lib
	$(CC) -shared $(CFLAGS) $^ -o $@ $(LDFLAGS)

bin/app: $(obj)
	@mkdir -p bin
	$(CC) $(CFLAGS) $^ -o $@ $(LDFLAGS)

testsrc := $(filter-out src/main.c,$(csrc)) $(wildcard test/*.c) $(wildcard test/**/*.c)
testobj := $(testsrc:%.c=obj/%.o)

bin/test: $(testobj)
	@mkdir -p bin
	$(CC) $(CFLAGS) $^ -o $@ $(LDFLAGS)

.PHONY: clean
clean:
	$(RM) -r obj
	$(RM) -r lib
	$(RM) -r bin

Quick Summary

(The real GNU make docs are here)

• $@: The path to the file produced by the current rule
• $^: The list of dependencies for the current rule